4 months ago
Eng, E&E Engrg
Business Unit UTC Aerospace Systems
Job ID 53910BR Date posted 09/19/City Phoenix
The UTC Re-Empower Program helps support talented and committed professionals as they rebuild their capabilities, enhance leadership skills, and continue their professional journey. Over the course of the 16-week program, experienced professionals will gain paid, on-the-job experience, have an opportunity to participate in sessions with leadership, develop personalized plans for success and receive coaching to guide their return to work experience. Upon completion of the program, based on performance, Re-Empower participants may have an opportunity to convert to a full-time role.
The first cohort of the UTC Re-Empower Program will run from January 22, 2018 – May 11, 2018.
Minimum Program Qualifications
To qualify for the UTC Re-Empower Program, candidates should:
Currently be on a voluntary break of at least two years or more
Have a minimum of five years of professional work experience
Have an interest in returning to work in a full-time position
Have an ability to attend the Re-Empower Program Orientation at UTC Headquarters in Farmington, CT on January 22 – January 24, 2018
Because of a strategic commitment, United Technologies Aerospace Systems (UTAS) created an Electronic Systems Center (ESC) headquartered in scenic Phoenix, AZ. The ESC supports a wide variety of UTAS aerospace products with state-of-the-art facilities and expertise. The ESC team designs, tests, builds, and supports electronic units and systems for all parts of the Enterprise. As part of the ESC the FPGA Design department develops flight firmware for a range of electronic controllers.
The FPGA Design Engineer will work with a global team of HDL developers, in Phoenix and India, to complete CPLD and FPGA designs, simulations, synthesis, floor-planning and lab integration for electronic control units for aerospace applications.
1. Follow DO-254 Level A program planning documentation and ensure CPLD/FPGA design team adheres to the plans.
2. Capture and document the customer flowed down functional requirements, and develop as well as document the derived requirements for FPGAs.
3. Design FPGA architectural diagrams; develop VHDL to implement the design critical functionality.
4. Develop sub-functions and test benches.
5. Perform engineering timing simulations and functional analysis.
6. Interface with the V&V team and Quality Engineers to support the creation of the DO-254.
7. The ideal candidate will be able to prioritize multiple requests in a fast-paced environment with impeccable attention to detail and accuracy while maintaining a pleasant and "can do" attitude.
8. The successful candidate must be willing to pitch in and do whatever is necessary to get the job done right.
Qualification: The successful candidate will be a highly motivated self-starter with strong written and oral communication skills and work well in a team environment.
* Proficient with HDL and using Mentor Modelsim.
* Experience with Actel, Xilinx, FPGAs and development tools.
* Excellent FPGA lab integration and troubleshooting knowledge.
* Excellent written and verbal skills
* Good computer skills with ability to learn new programs/software
* Ability to work as part of a multi-disciplined engineering team
* Ability to work under pressure and within time constraints
* Excellent organizational skills with ability to multitask amidst rapid change
Education: BS degree in Aerospace, Electrical, Systems, Computer Engineering, or Relevant. At least six (or four with Masters) years’ experience in VHDL or Verilog design for CPLDs or FPGAs in an Aerospace environment.
* Experience working within DO-254 DAL A certification program(s)
* Ability to design test benches.
* Experience with Mentor HDL Designer, Precision Synthesis, Questa and Req Tracer.
United Technologies Corporation is An Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age or any other federally protected class.