Digital ASIC design and verification. Candidates should have 10+ years of Digital ASIC design experience including verification. Candidate must demonstrate strong background with design architecture and detailed specification for DSP and Switch-based designs. Knowledge of ASIC development including architectural definition, detailed design implementation using SystemVerilog, and functional verification using SystemVerilog. Knowledge and competency of UVM is a plus. Experience with IBM/GF technology a plus. Candidate must be able to take high-level architectural documentation along with algorithm description and implement DSP functions for decimation, interpolation, general filtering, up-down conversion, digital beamforming, channelization, and be able to come up with mathematical models in C or SystemVerilog to verify design implementation. Candidate must be knowledgeable in concepts of static timing analysis, synthesis, and able to develop and run scripts and Makefiles. Candidate must be able to thrive in working within a fast-paced environment and work well in a team of ASIC engineers and Subsystem engineers. Candidate must demonstrate history of 1st pass success with ASIC designs.
Bachelor's degree with 14 or more years' experience, Master's degreee with 12 or more years' experience or PhD with 9 or more years' experience. Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry.